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Binary Counter.

Binary Counter.

A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, and so on down to the fourth cell. This produces a binary number equal to the number of cycles of the input clock signal. This device is sometimes called a "ripple through" counter. The same device is useful as a frequency divider.

Sequential Circuit

Sequential circuits

In general, we define a synchronous sequential circuit, or just sequential circuit as a circuit with m inputs, n outputs, and a distinguished clock input. The description of the circuit is made with the help of a state table.
We have intentionally simplified our definition of sequential circuit. With our definition, the number of different states of the circuit is completely determined by the number of outputs. A more general definition separates the concept of output and the concept of state. Four our purposes, the additional generality is not needed, and we stall stick with our simple definition.
The same "goodness" criteria apply to the design of sequential circuits as to combinatorial circuits, i.e., number of transistors, speed, power consumption etc. Thus, as with combinatorial circuits, we are not going to discuss methods for obtaining optimal circuits, but only a very general method that in the worst case may waste a large number of tansistors. However, the purpose is not to turn the students into circuit designers, but to give them an idea of how sequential circuits work.
For a sequential circuit with m inputs and n outputs, our method uses n D-flip-flops (one for each output), and a combinatorial circuit with m + n inputs and n outputs. Here is the general structure of the resulting circuit:
Since we are using D-flip-flops, the outputs of the circuit after the next clock pulse is exactly the same as the output of the combinatorial circuit. We can therefore use our general method for building combinatorial circuits, this time applied to the state table of the sequential circuit.
As an example, let us construct a 2-bit counter with an input indicating whether to count up or down (0 means down and 1 means up). The counter should stop at 00 when counting down and at 11 when counting up. Here is the state table for such a counter: u/d y1 y0 y1' y0' -------------------- 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1
With our general method, all we need to do is to build a sequential circuit from the truth table corresponding exactly to this state table. Here is the resulting circuit:

Shift Register

Shift-register circuit

A shift-register circuit. The PMOS transistor includes a first gate for receiving an inverted output signal output from a previous stage shift-register unit, a first source for receiving an output signal from the previous stage shift-register unit, and a first drain. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first source, a third drain coupled to the second source and a third source coupled to the ground level. The third NMOS transistor includes a fourth gate coupled to an output of a next stage shift-register unit, a fourth drain coupled to a connection point of the second gate and the capacitor and a fourth source coupled to the ground level. The first inverter is coupled to a connection point of the first NMOS transistor and the second NMOS transistor to output an inverted output signal. The second inverter is coupled to the first inverter to output an output signal.
Representative Image:

Decoder Circuit

Decoder Cuicit:

A decoder circuit is disclosed for use with a storage module having storage cells constructed from MOS transistors arranged between word lines and bit lines. In order to select one of the word lines or bit lines, control inputs of the decoder transistors are fed with n address signals in negated or non-negated form and a decoder output signal is emitted on a decoder output line which connects the one terminals of the controlled paths of the decoder transistors. In the decoder, n-1 decoder transistors are arranged with their controlled paths in parallel and a further decoder transistor is provided whose control input is supplied with an address signal in negated form and whose controlled path is arranged between a connection line which connects the one ends of the controlled paths of the n-1 decoder transistors and an operating voltage. An additional decoder transistor is provided whose control input is fed with the address signal in non-negated form and whose control path is connected between the operating voltage and a second connection line which connects the other ends of the controlled paths of the decoder transistors. Both the first and second connection lines form respective decoder output lines for the selection of a word/bit line.