Decoder Cuicit:
A decoder circuit is disclosed for use with a storage module having storage cells constructed from MOS transistors arranged between word lines and bit lines. In order to select one of the word lines or bit lines, control inputs of the decoder transistors are fed with n address signals in negated or non-negated form and a decoder output signal is emitted on a decoder output line which connects the one terminals of the controlled paths of the decoder transistors. In the decoder, n-1 decoder transistors are arranged with their controlled paths in parallel and a further decoder transistor is provided whose control input is supplied with an address signal in negated form and whose controlled path is arranged between a connection line which connects the one ends of the controlled paths of the n-1 decoder transistors and an operating voltage. An additional decoder transistor is provided whose control input is fed with the address signal in non-negated form and whose control path is connected between the operating voltage and a second connection line which connects the other ends of the controlled paths of the decoder transistors. Both the first and second connection lines form respective decoder output lines for the selection of a word/bit line.
